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New Method for On-chip Decoupling

IP.com Disclosure Number: IPCOM000065717D
Original Publication Date: 1985-Jul-01
Included in the Prior Art Database: 2005-Feb-19

Publishing Venue

IBM

Related People

Authors:
Brigida, DJ Pokorny, WF Vogl, NG [+details]

Abstract

A serious problem with dense and fast FET memories is high current requirements in short periods of time. These DI/DT problems are also encountered to a lesser extent on chips that are not as dense or as fast. A method for on-chip decoupling provides a way to decouple along the VH bus on-chip without forfeiting as much area as would otherwise be required. The method involves forming a thin oxide capacitor 11 along as much of the VH bus as possible (Fig. 1), thereby diminishing the amount of additional silicon needed for decoupling capacitors. On slower and less dense memories, the method itself may give adequate decoupling. The VH bus may include a strip of polysilicon POLY or other conductive material and a metal layer Ml stitched to the POLY at appropriate locations. An N+ region is connected to an M1 ground bus.