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This article describes a method and apparatus for expanding the addressing range of a microprocessor by providing more address lines.
English (United States)
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Address Range Expander for a Microprocessor
This article describes a method and apparatus for expanding the addressing
range of a microprocessor by providing more address lines.
The circuit for expanding a microprocessor's address range is shown in the
schematic with an N-bit register, the Extended Address register 2, that is mapped
into I/O address space 3. This register provides the N-bits of extended address
(EXT ADR). The data bus (DATA) 4 is latched into a D-type flip flop 5 when a
given I/O address is decoded (i.e. ADR 6 activates the output of the DCD block 7) along with data strobe 8 (DS), address strobe (AS) 9 and write (WR) 10 being
active. The design assumes that DS, AS and WR all become active after the
ADR 6 and DATA lines 4 contain valid data.
The address lines are increased by this design from M to (M + N) lines; an
increase in memory address space from 2M to 2(M N). The I/O address space is
similarly increased, with the exception that one I/O address is required for the
EXT ADR register.
If the EXT ADR lines are used as high order memory address lines, then
these lines can be used to point to any of 2N pages, each page being 2M in
length. Changing pages is accomplished by a simple I/O write by the
microprocessor (mP) to the EXT ADR register 2. All subsequent memory
accesses will be made into this new page. Note that a reset of the mP forces the
EXT ADR register 2 to point to the zero page.