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Circuit for Testing Word Line Levels in Mtl/I2l Memories Disclosure Number: IPCOM000065837D
Original Publication Date: 1985-Oct-01
Included in the Prior Art Database: 2005-Feb-19

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Barsuhn, H Klink, E Najmann, K Wernicke, FC [+details]


A test circuit is proposed that permits detecting defective word lines by means of a simple DC test, without using additional pads and circuitry. For the compact wiring of circuit elements, present VLSI semiconductor chips necessitate both a high integration density in and several metal layers on the silicon. The susceptibility to interlevel shorts, leading to an undesired conductive channel, increases with the number of metal layers used. If such an undesired channel lies above word lines, it does not necessarily lead to serious defects that are readily detected by testing. A word or bit line WL/BL short, i.e., a short- circuit between the bit line (first metal) and word line (second metal) in an MTL array, similar to that described in the [*], increases the word line potential.