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Tristate Bus Testing Scheme

IP.com Disclosure Number: IPCOM000065859D
Original Publication Date: 1985-Oct-01
Included in the Prior Art Database: 2005-Feb-19

Publishing Venue

IBM

Related People

Authors:
Mitby, JS [+details]

Abstract

If a tristate net is not brought off chip, there is no practical way to determine whether all of the tristate drivers can be gated into the high-Z state. By adding FETs Tl thru TN, a tester can determine if any of the N nets are not in the high-Z state. The test is done as follows: l. With TEST low (Tl thru TN are off), each net can be tested for a stuck at l or stuck at 0 fault in the normal way. 2. With TEST high and tristate drivers gated to high Z, Tl thru TN are on, and a tester can now detect if any of the N nets are not high Z by checking the voltage at the SENSE output.