Internal PLA Clock Generator
Original Publication Date: 1985-Oct-01
Included in the Prior Art Database: 2005-Feb-19
The circuit shown in Fig. 1 generates an internal clock for the AND array of a programmable logic array (PLA). The clock requirements are that the output (CLK) cannot switch before the slowly falling input (VIN) falls below the threshold voltage of an N-Channel device (VTN).