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System of Flags for Indicating Multiple Requests for an Interruption Disclosure Number: IPCOM000065942D
Original Publication Date: 1985-Dec-01
Included in the Prior Art Database: 2005-Feb-19

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Wu, BH [+details]


In some data processing systems, a peripheral device can connect to central processor memory through any one of several paths that are each controlled by a different channel engine. At certain stages of an I/O operation, the device requests an interruption and the channel engine posts the interruption by setting a bit that signals that the interruption is pending. An interruption handling processor (called an I/O processor) resets the interruption bit when it handles the interruption request. The channel engine can not post another interruption for the device until the pending interruption request has been cleared. However, a device that has an interruption pending through one channel can request an interruption through another channel.