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Multiple Counters In Array Logic

IP.com Disclosure Number: IPCOM000065998D
Original Publication Date: 1979-Jan-01
Included in the Prior Art Database: 2005-Feb-19

Publishing Venue

IBM

Related People

Authors:
Allgood, HB Stucka, SE [+details]

Abstract

This article describes a method of utilizing an m and an n bit binary counter implemented in a PLA (programmable logic array) to provide multipurpose counting functions. The counters can be used either separately as two independent counters, or working together for matrix type control, or as one (m + n) bit counter. Proper PLA implementation allows all three modes of operation in a single PLA chip with only a minimal increase in hardware used over the simple (m + n) bit counter. Simple counter design in the PLA requires one input, one output, and one wordline for each bit of the binary counters. In addition, a count control input is required for each separate counter.