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This cell layout (Fig. 2) shows how a previously wire-limited cell can be improved for better wireability.
English (United States)
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Schottky Transistor Logic Cell Image
This cell layout (Fig. 2) shows how a previously wire-limited cell can be
improved for better wireability.
The previous cell (Fig. 1) used six wiring channels for six Schottky diode
positions. With a high fan-out, this cell would block off its own wiring channels.
By decreasing the first-level wiring channel spacing and allowing only
nonadjacent vias and nonadjacent Schottky diodes, more channels can be added
to the cell. In addition, the cell was lengthened to provide 10 wiring channels
over the Schottky area.
The advantage of nonadjacent Schottky diodes is that it prevents a cell from
becoming blocked from a high fan-out condition.
By lengthening the cell, the total number of cells on the chip will be less, but
this can be offset with a greater number of cells being wired.
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