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This is an array chip clocking technique for minimizing standby power by controlling the relationship between the array phase clocks.
English (United States)
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System Clocking Control For CCD Memories
This is an array chip clocking technique for minimizing standby power by
controlling the relationship between the array phase clocks.
In charge-coupled device (CCD) memory applications the data has to be
recirculated to be maintained. During standby or idle conditions the recirculation
occurs at a lower frequency than the selected or accessed state. This results in
a reduction in power since only that portion which is selected is clocked at the
faster frequency. Since most of the power at the system level is in the
unselected or standby state, this power should also be kept to a minimum.
Fig. 1 shows the normal clocking relationship between the phases for
selected and unselected chips. Fig. 2 depicts the technique of modified clocking
control of this article for unselected chips. There are two methods of this
operation depending upon the phase clock type used for clocking. Case 1
minimizes the power for a driver with high power in the up level, while case 2
minimizes the power for a driver with its high-power state in the down level.
As a result of modifying the relationship between phase clocks to achieve the
low-power state of the driver, a reduction in power levels can be obtained in the
standby or recirculate operation of the memory.
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