Clock Pulse Stretching Technique
Original Publication Date: 1979-Jan-01
Included in the Prior Art Database: 2005-Feb-19
The attachment of different speed memories in a synchronous manner to a data processing unit while maintaining pre-established internal timing relationships within the processing unit is facilitated by the use of extended R0S (read-only store) bits and corresponding logic to selectively delay the stepping of the clock ring to produce the next clock pulse. For example, a slower, less costly memory unit can be attached to a data processing machine designed to accommodate higher speed memory elements. All performance areas where the slower memory unit is not accessed are kept at their original high speed values. All edges on clock relationships are maintained exactly as in the original design whether or not the slower memory unit is accessed.