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Testing LSI Chips

IP.com Disclosure Number: IPCOM000066073D
Original Publication Date: 1979-Jan-01
Included in the Prior Art Database: 2005-Feb-19

Publishing Venue

IBM

Related People

Authors:
Remshardt, R Schettler, H Schumacher, H Zuehlke, R [+details]

Abstract

For rapidly testing LSI (large-scale integration) chips with logic circuits, the chip is divided into several, for example, four, regions. Each region has its own supply voltage connection. Thus, there are four regions which can be linked to the supply voltage independently of each other. To test the circuits of a region, those regions the output lines of which lead to the region to be tested are provided with a reduced supply voltage. As a result, all transistors connected to the output lines of such regions become nonconductive, and the reduced supply voltage at a positive level is available on the output lines.