Fabrication of Narrow Signal and Bus Lines on a MOSFET Chip
Original Publication Date: 1979-Jan-01
Included in the Prior Art Database: 2005-Feb-19
Much of the area on the surface of a MOSFET (metal oxide semiconductor field-effect transistor) chip is occupied with interconnect signal lines. In the prior art, photolithographic limitations require a minimum of, for example, six-micron line width and line spacing so that parallel lines can lie on a minimum of twelve-micron centers. The figures show steps using reactive ion etching which results in equal conductivity lines of only three to four microns in width and which can be placed on six- to eight-micron centers.