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Two-Way NOR Circuit in Double Layer Polysilicon FET Technology

IP.com Disclosure Number: IPCOM000066081D
Original Publication Date: 1979-Jan-01
Included in the Prior Art Database: 2005-Feb-19

Publishing Venue

IBM

Related People

Authors:
Devine, WT Henry, DL Wang, PP [+details]

Abstract

Fig. 1 shows a schematic of an FET (field-effect transistor) NOR circuit. Fig. 2 shows an implementation of this circuit utilizing a square geometry FET device having a lower polysilicon gate layer 11 and an upper polysilicon gate layer 13 separated by silicon dioxide. The common grounded source region 15 surrounds a channel region under the gate layers 11 and 13, and is likewise insulated therefrom. A common drain region 17 concentrically located within source region 15 presents a significantly smaller area under gate layers 11 and 13, thereby reducing capacitance. Metallization 19 provides a connection between drain 17 and load resistor R.