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This checking technique utilizes the dependency of concentrated checkers on the technology.
English (United States)
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Checking Multi-Terminal Circuit Entities With Fixed Three-Terminal
This checking technique utilizes the dependency of concentrated checkers
on the technology.
Software for conventional logical-to-physical checking is based on an
analysis of the mask shapes used to build the hardware. The physical design of
the item to be manufactured describes chips, boards, cards or any collection of
shapes. In the normal mode of operation, the software is arranged to look for
shapes that make up entities, for example, FET devices, and then stores their
terminal names. For example, once a FET device is recognized and the
characteristics of its terminals are known, a record is created in a table. This
record has three fields. The first two fields are in diffusion connection, and the
third is its gate connection. In the case of the existing software programs, the
entities have only three terminals. Each entry in the stored table is assumed to
be a device by the program that will be doing the comparing of the master device
list and the entity device table. Logical-to-physical checking is done by doing a
graph-to-subgraph compare, where the graph is the set of all table entries and
the subgraph is a small set of entities specified by a master list or logical
description. In existing software checkers, the entries are FET devices and the
subgraphs are circuits like NOR gates. These subgraphs range in size from 1 to
20 or more devices, as shown in Fig. 1.