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Test systems for high speed logic require precisely timed pulses. The reason for this is that these systems must determine whether or not pulses from the logic under test arrive at specified times.
English (United States)
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Cycle Selecting Delay Function For Dynamic Testing
Test systems for high speed logic require precisely timed pulses. The
reason for this is that these systems must determine whether or not pulses from
the logic under test arrive at specified times.
Shown above is a circuit which allows appropriate high speed timing of a
dynamic enable pulse with respect to a basic clock pulse TO and an expected
value pulse. Such a circuit can be implemented on a single integrated circuit
chip for high speed operation. The circuit includes four polarity hold, latches
PH1 to PH4, each of which has a data input D and a clock input C, two set-reset
latches L1 and L2, a delay block DLY, AND gates 1 and 2, OR circuits 3 and 4,
and inverters 5 to 8.
Depending on cycle time duration, the dynamic enable pulse can occur in the
same cycle as the dynamic expect pulse or it can occur in the next cycle. The
circuit shown is capable of dynamically determining when the cycle enable pulse
will occur. The circuit applies valid expect data at that time.
AND circuit 1 and latch L1 (reset over set) insure proper operation of the
circuit when TO and dynamic enable are coincident at either the rising edges or
falling edges. The block delay DLY in the dynamic enable line insures that
dynamic enable occurs after dynamic expect.
The significant feature of this circuit is that it makes the dynamic operation of
the level detectors independent of the accumulative system delays with regard to
the expect and e...