Browse Prior Art Database

Wirability Enhancement

IP.com Disclosure Number: IPCOM000066270D
Original Publication Date: 1979-Feb-01
Included in the Prior Art Database: 2005-Feb-19

Publishing Venue

IBM

Related People

Authors:
Jarvela, RA Jesrani, MJ [+details]

Abstract

The drawing illustrates a cross-sectional view of a multilayer ceramic substrate comprised of four voltage reference planes 1 and three pairs of X-Y signal planes 2. The voltage reference plane pattern 3 allows normal signal vias 4 and discretionary vias 5 to pass through them. A normal signal via 4 to signal via 4 net connection is accomplished by entering the substrate from above and traversing downward to the first available X direction signal plane, then connecting through a line and a discretionary via from the X plane to an adjacent Y plane, then through a line to the second signal via 4 back to the top surface.