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Direct Coupled Inverter Disclosure Number: IPCOM000066281D
Original Publication Date: 1979-Feb-01
Included in the Prior Art Database: 2005-Feb-19

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Battista, MA Culican, EF Lohrey, FH Park, SJ [+details]


Two basic requirements of polarity-hold latch designs are that the latches be DC hazard free (independent of input rise and fall times) and glitchless (will not generate false output pulses). The design of the Clock Driver, which generates the signals controlling the latches, primarily determines if these two requirements are met.