Browse Prior Art Database

Multi-Function Latch For Shift Register Latches In Schottky Transistor Logic

IP.com Disclosure Number: IPCOM000066282D
Original Publication Date: 1979-Feb-01
Included in the Prior Art Database: 2005-Feb-19

Publishing Venue

IBM

Related People

Authors:
Das Gupta, S Diepenbrock, J [+details]

Abstract

A design structure called Level Sensitive Scan Design (LSSD) has been explained in U.S. Patent 3,783,254. The purpose of LSSD is to enhance testability of complex networks. This is achieved by requiring all latches in any sequential network to be part of shift register latches (SRLs). These SRLs are tied together to form one or more shift registers whose contents are controllable from scan-in primary inputs (PIs) and scan clocks, and observable at scan-out primary outputs (POs). In effect, these shift registers logically break the feedback loops in any sequential network so as to reduce the problem of test generation in a sequential network to that of a combinational one.