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Connection Of PNP Transistors In Master Slices

IP.com Disclosure Number: IPCOM000066287D
Original Publication Date: 1979-Feb-01
Included in the Prior Art Database: 2005-Feb-19

Publishing Venue

IBM

Related People

Authors:
Bonnet, Y [+details]

Abstract

In most designs of circuits on master slices, NPN transistors have their collectors connected to the most positive voltage C++, their emitters to the least positive voltage EO, and their bases to a mid-range positive voltage B+. The structure of lateral NPN devices allows easy wiring even when a plurality of devices are connected in parallel. Fig. 1A shows lateral NPN devices having their bases connected together without requiring any underpasses.