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A test sequence is to be used for detecting the disturb condition during the write operation in a semiconductor memory comprising Harper cells.
English (United States)
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Storage Cell Disturb Test For Harper Cell Memory
A test sequence is to be used for detecting the disturb condition during the
write operation in a semiconductor memory comprising Harper cells.
The test sequence applies to a memory organized as a matrix of rows and
columns. Three cells O, K and N are represented in the drawing. The cells in a
column are connected to left and right bit lines LBL and RBL, respectively. The
cells in a row are connected to word line WL, cell O to line WLO, cell K to WLK
and cell N to line WLN.
Line drivers LDO to LDN connected to lines WLO to WLN allow the selection
of a row of cells at corresponding addresses O to N.
Once one row has been selected, the write operation in the selected cells is
performed through transistors TSAL and TSAR.
In such a memory the most critical situation occurs when the memory
contains zeros or ones in all the positions except those of one word and this word
is to be set to the same value as the other words in the memory.
These unfavorable conditions are tested through the following
sequence: Step 1 - a zero is written in all the memory positions
- the entire memory is read
- a one is written in the position at address 0
- address 0 is read
- a zero is written in the positions at address 0
- the entire memory is read
Step 2 - a one is written in the positions at address 1
- address 1 is read