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The dynamic single bit partitioner shown above and described below generates dynamically two outputs which are capable of driving substantial capacitive loads with essentially no DC power consumption.
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Dynamic Single Bit Partitioner
The dynamic single bit partitioner shown above and described below
generates dynamically two outputs which are capable of driving substantial
capacitive loads with essentially no DC power consumption.
Turning now to Fig. 1, during phase R ( phi R) time, nodes N1, N2, N3 and
N4 are precharged to the supply voltage VDD via the load device transistors T3
and T7. Node N5, however, will charge to a threshold voltage (VT) which is less
than VDD because device T2 is in the saturation region. A special feature of this
circuit is that the input "IN" need only be as high as the potential of node N5, that
is, "IN" > (VDD - VT). When phase phi R goes to ground or low, and with "IN" at
ground, node N5 will remain essentially at VDD - VT while nodes N3 and N4 will
discharge through devices T6 and T8. In this connection, it should be noted that
there is a minimum time T0 (Fig. 2) for this action to take place before phase phi
1 comes up.
When phase phi 1 does come up, node N1 is bootstrapped high via the
inversion layer capacitor CBS1, and a pulse appears at the output inp of the bit
partitioner. Device T4 is used strictly to decrease the parasitic capacitance on
the gate of device T5 so that a higher bootstrap ratio CBS1/CBS1+CP1 may be
achieved. Inasmuch as node N5 is high at this time, node N4, as well as output
inp, will be kept at ground.
When the input "IN" is high, the bit partitioner operates as follows: First, if
node N5 is already high, as phase phi R rises, it capacitively couples its charge
to node N5 via t...