Two-Mask Mesa Thin Film Transistor
Original Publication Date: 1979-Feb-01
Included in the Prior Art Database: 2005-Feb-19
A previous article in the IBM Technical Disclosure Bulletin 21, 1668 (September 1978) described a technique for manufacturing a mesa thin film transistor array which involves the deposition of source-drain metallurgy, the deposition of successive layers of semiconductor, insulator, and gate metal, selective etchings to define the devices, sputter passivation, and, finally. the etching of the contact vias.