Latch Circuit For Retaining Very Short Duration Data
Original Publication Date: 1979-Feb-01
Included in the Prior Art Database: 2005-Feb-19
This article describes a new latch circuit designed to 'catch' short duration data on an open-collector or three-state bus. The data is characterized by Fig. 1(a), where it is known that the data becomes good somewhere between A and B, and the 'data good window' C-D is very short (equivalent to a few gate delays). In this situation it is impossible to strobe the data into a conventional latch (JK, polarity hold or Dtype) as the position of the data between A and B is unknown and C-D is very short.