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Double Polysilicon Dynamic Random Access Memory Cell With Increased Charge Storage Capacitance

IP.com Disclosure Number: IPCOM000066375D
Original Publication Date: 1979-Feb-01
Included in the Prior Art Database: 2005-Feb-19

Publishing Venue

IBM

Related People

Authors:
Rideout, VL [+details]

Abstract

In one-device dynamic memory cells it is desirable to maximize the storage capacitance per unit area without increasing the cell area or the bit line capacitance. The storage capacitor has two primary components: one related to the thin dielectric insulator, and the other to the depletion region in the semiconductor bulk. The insulating layer thickness is dictated by dielectric breakdown considerations. The depletion layer capacitance can be increased by providing a double doped layer consisting of a shallow N+ region surrounded by a deeper P+ region (*), as shown in Fig. 1. Although extra fabrication steps are required for this "Hi-C" random-access memory cell, the storage capacitance can potentially be doubled without increasing the cell area.