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Processor-To-Processor Intercommunication Employing A Common Storage Module Disclosure Number: IPCOM000066441D
Original Publication Date: 1979-Mar-01
Included in the Prior Art Database: 2005-Feb-19

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Davidson, KA Parsons, RL Reed, DG Saavedra, F Whitmer, DE [+details]


A multiprocessor system includes four processors or basic storage modules BSM 0 to BSM 3. The processors are interconnected by a pair of tag lines - attention (A) and response (R). For example, line AR01 is the attention response line from BSM 0 to BSM 1, whereas RA01 is the response to attention line of BSM 0 to BSM 1. In looking for communications initiated by BSM 1, then the reverse is true, RA01 becomes AR10 while AR01 becomes RA10. This notation will become apparent from a continued reading of this article.