Browse Prior Art Database

Hierarchical High Level Designer Tester Interface

IP.com Disclosure Number: IPCOM000066451D
Original Publication Date: 1979-Mar-01
Included in the Prior Art Database: 2005-Feb-19

Publishing Venue

IBM

Related People

Authors:
Zobniw, LM [+details]

Abstract

Printed-circuit boards (PCB) containing arrays, microprocessors, programmable logic arrays, and random logic may require functional approaches to testing. New generation testers have inherent capabilities to process high-level (high) commands at functional speeds, for example, random-access memory's functional characteristics tailor random-access memories to high-level testing. A conventional single input change test strategy would require a large number (multi-million) of test patterns with long test times. Applying functional tests with high-speed buffers greatly decreases test time and data volume. This methodology processes high test data from PCB designer to the tester.