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Processing For A Lateral PNP Transistor In The Submicron Range

IP.com Disclosure Number: IPCOM000066488D
Original Publication Date: 1979-Mar-01
Included in the Prior Art Database: 2005-Feb-19

Publishing Venue

IBM

Related People

Authors:
Wieder, AW [+details]

Abstract

Enhanced oxidation of N+ material and equal etching rates of resist and polysilicon permit processing of PNPs in the submicron range. The PNP transistors have a planarized structure that has minimum capacitances and emitterbase and collectorbase capacitances that are equal. A polysilicon emitter provides gettering capability. Good quality thermal oxide surrounds and passivates all junctions. The process is also extendable to permit the fabrication of PNPs and NPNs in a common substrate.