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Logic Circuit Simulation With Delay Variations

IP.com Disclosure Number: IPCOM000066520D
Original Publication Date: 1979-Mar-01
Included in the Prior Art Database: 2005-Feb-20

Publishing Venue

IBM

Related People

Authors:
Savkar, AD Shah, HG [+details]

Abstract

Logic circuits are commonly evaluated using simulation procedures that assign delays (generally worst-case delays) to various basic signal processing operations. Overall circuit operation is then analyzed by applying test patterns of inputs to the simulated circuit and examining the outputs to determine if the correct response occurs. A more realistic evaluation is achieved by randomly selecting delays for each basic processing operation according to empirically developed respective delay distribution curves (see figure).