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MTL Structure With Vertical PNP Transistor

IP.com Disclosure Number: IPCOM000066591D
Original Publication Date: 1979-Mar-01
Included in the Prior Art Database: 2005-Feb-20

Publishing Venue

IBM

Related People

Authors:
Dumke, WP [+details]

Abstract

The conventional merged transistor logic (MTL) structure has two transistors, one of which is a pnp lateral transistor that has a collector region which is continuous with the base region of a second transistor, an upside down npn multi-collector device. This device is shown in Fig. 1. The lateral transistor has both a low current gain and, because of a large base width ((Image Omitted) 2Mum), a poor high frequency response.