MTL Structure With Vertical PNP Transistor
Original Publication Date: 1979-Mar-01
Included in the Prior Art Database: 2005-Feb-20
The conventional merged transistor logic (MTL) structure has two transistors, one of which is a pnp lateral transistor that has a collector region which is continuous with the base region of a second transistor, an upside down npn multi-collector device. This device is shown in Fig. 1. The lateral transistor has both a low current gain and, because of a large base width ((Image Omitted) 2Mum), a poor high frequency response.