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Simultaneous Unit and Zero Delay Mode Fault Simulation to Provide Decreasing Redundant Simulation of Gates in Arbitrary Sequential Circuits Fault Simulation Disclosure Number: IPCOM000066605D
Original Publication Date: 1979-Mar-01
Included in the Prior Art Database: 2005-Feb-20

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Related People

Cesar, CL Cha, CW Donath, WE [+details]


This article describes a method for fault simulation of arbitrary sequential networks, which avoids excess activity of blocks within combinatorial networks during simulation. The essence of this method is to do unit and zero delay mode simulation at the same time.