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This is an improved sense latch for charge-coupled devices, providing improved sensitivity and performance by making devices 1 and 2 depletion mode devices.
English (United States)
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Sense Latch For Charge Coupled Devices
This is an improved sense latch for charge-coupled devices, providing
improved sensitivity and performance by making devices 1 and 2 depletion mode
The figure illustrates a "load steered" flip-flop for use as a sense latch for
charge-coupled devices. The use of a "load steered" flip-flop prevents the data
node from being discharged to ground and injecting charge back into the charge-
coupled device channel. Previously, such a circuit was fabricated with all
enhancement devices. The basic operation remains the same, with devices 1
and 2 being depletion mode devices. The phase 1 clock at the gate of field-
effect transistors 5 and 6 turns them on, bringing the data node and reference
node to the same potential. The phase 2 clock at the gate of field-effect
transistor 7 operates to establish a desired race condition.
Prior to the occurrence of an input signal at the data node, the clocks (phase
1 and phase 2) turn off devices 5, 6, and 7 so that the appearance of a charge at
the data node tends to condition either device 1 or device 2 into a higher state of
conduction. This, in turn, conditions one of the cross-coupled field-effect
transistors 3 or 4 into a higher state of conduction. At the occurrence of an up-
level clock phase 2 signal at the gate of field-effect transistor 7, it is turned on,
and one of transistors 3 and 4 conditioned into a higher state of conduction
"wins" the race, bringing its corresponding out...