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Use Of Ge in Si Crystals To Improve The Yield Of Integrated Circuit Chips

IP.com Disclosure Number: IPCOM000066802D
Original Publication Date: 1979-Apr-01
Included in the Prior Art Database: 2005-Feb-20

Publishing Venue

IBM

Related People

Authors:
Dumke, WP Woolhouse, GR [+details]

Abstract

In the processing of silicon (Si) wafers involved in the manufacture of Si integrated circuit chips, there are several steps which can cause local strains and deformation or crystalline defects in the Si. Such damage to the wafers is one of the prime factors in reducing the yield of good chips. Examples of such strains are (1) those produced by thermal gradients during wafer cooling and (2) those strains around the edges of layers of SiO(2) and Si(3)N(4). The first example may produce permanent warpage of the wafer through the generation of dislocations, whereas the second produces damage in the form of dislocation complexes resulting in defective devices.