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Multiplexing With Functional Loop Logic

IP.com Disclosure Number: IPCOM000066815D
Original Publication Date: 1979-Apr-01
Included in the Prior Art Database: 2005-Feb-20

Publishing Venue

IBM

Related People

Authors:
Faris, SM [+details]

Abstract

In the Josephson junction environment, Functional Loop Logic (FLL) provides high speed and density especially for implementing complex functional blocks, such as decoders, full adders and comparators. This article shows the use of the FLL concept to construct multiplexers and demultiplexers which are necessary functional blocks for controlling traffic in a signal processor. Such functional blocks also benefit from the density and high speed of FLL so they can be strategically placed in a package where time saving is crucial.