Automatic Timing And Resetting of Josephson Junction Memory Arrays
Original Publication Date: 1979-Apr-01
Included in the Prior Art Database: 2005-Feb-20
Present memory arrays operate by driving DC currents into long loops which eventually have to be reset. One has to insure that reset gates are not activated while current is still being transferred because loops may be caused to hang up in the voltage state. Therefore, timing is crucial. Normally, clocking circuitry is necessary and has to be designed to obtain the shortest read and write cycles and yet avoid fault modes. This article describes a DC-powered timing circuit that is capable of automatic resetting of long loops without having to derive clock pulses in the middle of a memory cycle. Instead, the present circuit is set at the beginning of every cycle by a readily available pulse which initiates all other components of the memory chip.