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The extrinsic base resistance of a vertical bipolar transistor is significantly reduced by the use of a process to define a base contact which is self-aligned to the emitter.
English (United States)
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Reduction Of Extrinsic Base Resistance By Use Of Self-Aligning Base
The extrinsic base resistance of a vertical bipolar transistor is significantly
reduced by the use of a process to define a base contact which is self-aligned to
The partially completed NPN transistor structure of Fig. 1 comprises N+
subcollector 1 in P- substrate 2, recessed oxide 3 and 4 and P isolation region 5
which extends from oxide isolation 3 into substrate 2. The structure further
includes N+ reach-through 6, N- epi layer 7, base region 8 and emitter region 9.
Photoresist layer 10 is patterned to expose the base area of the transistor.
The masked structure is thermally oxidized, the oxide growing at a faster rate
over heavily doped emitter 9 than over less doped base 8, as shown by thicker
oxide region 11 and thinner oxide region 12 in Fig. 2, which is an enlarged view
of the base region. CVD (chemically vapor deposited) oxide 13 is deposited over
the grown oxide.
The oxide 13 is reactively ion etched to remove material down to about 50
nm below the original level of thermal oxide 11, leaving residual CVD regions 14
extending a fixed distance on either side of oxide 11, as shown in Fig. 3.
Platinum base contact deposit 15 is made, using regions 14 as a mask, and the
entire structure is covered by deposited oxide 16 and silicon nitride 17. Contact
openings are formed as shown in the final structure of Fig. 4.