Isolated Complementary Bipolar Transistors On Same Chip With Enhanced NPN Performance
Original Publication Date: 1979-May-01
Included in the Prior Art Database: 2005-Feb-20
In a process for making complementary bipolar transistors where N+ subcollector 1 of the NPN transistor interfaces with P+ isolation region 2 on N- substrate 3, the capacitance effect of the N+/P+ junction 4 is eliminated by electrically short circuiting that junction, i.e., placing P+ region 2 and N+ region 1 at the same potential. P+ region 2 is connected to N+ region 1 via P+ reach-through regions 5 and 6, metallization 7, N+ collector contact region 8 and N epi 9.