Browse Prior Art Database

OR Circuit To Reduce Loading On PLA or Array

IP.com Disclosure Number: IPCOM000066910D
Original Publication Date: 1979-May-01
Included in the Prior Art Database: 2005-Feb-20

Publishing Venue

IBM

Related People

Authors:
Delahanty, RJ Grice, D Washburn, W [+details]

Abstract

As the number of devices on an OR array line increase, the capacitive loading on the line increases. Because the speed at which the OR array output can respond is inversely proportional to the capacitive loading, larger devices having more current capacity are often used in the OR array. Increasing the device size has two negative effects: (1) the power dissipated in the array increases and (2) the width of both the OR and AND array must increase to accommodate the larger devices. Of course, increasing the device size also increases each devices intrinsic capacitance, and therefore a point of diminishing return is reached at which further increases in device size offer no increased speed.