Synchronous Priority Selection
Original Publication Date: 1979-May-01
Included in the Prior Art Database: 2005-Feb-20
This article concerns a technique and logical circuit arrangement for selecting one among a plurality of circuits (or terminals) contending for access to a shared resource (e.g., a data communication bus). Polling control circuit 1 and circuit nodes (or terminals) 2-4 are linked in a polling loop 5 (Fig. 1). A common clock signal source 6 supplies clock (CLK) signals via line 7 to control circuit 1 and the contending nodes 2-4. As suggested by dotted lines preceding "node N" at 3 and following "node N + 1" at 4, nodes 2-4 may comprise an arbitrary number of nodes.