Received Data Transfer System
Original Publication Date: 1979-May-01
Included in the Prior Art Database: 2005-Feb-20
The received data transfer system described in U.S. Patent 4,065,810 employs a cycle steal (CS) pointer register in the processor and a single received status list. Each time status is required to be recorded in the list the channel hardware causes an interrupt to the control program to be initiated. This notifies the control program of the new status entry in the list. In certain instances, such as full duplex data transmission, a single finite list may prove to be inadequate since received messages may be concatenated, not providing an opportunity as in half-duplex transmission, for processing the received status list and reinitializing the registers for handling the same.