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Method Of Fabricating High-Performance IGFET Structures With Highly Controllable Submicron Effective Channel Lengths

IP.com Disclosure Number: IPCOM000066982D
Original Publication Date: 1979-May-01
Included in the Prior Art Database: 2005-Feb-20

Publishing Venue

IBM

Related People

Authors:
Bassous, E Ning, TH [+details]

Abstract

This article describes a process for the fabrication of D/MOS-type FET (field-effect transistor) structures. Known techniques utilize ion implantation for source and drain in order to eliminate the parasitic capacitance associated with conventional D/MOS. In addition, by controlling the undercut of a tungsten film which serves as a mask for a subsequent ion implantation step, the effective channel length of the high threshold voltage (V(T)) region of the device can be made very small and precise.