Browse Prior Art Database

Dynamic Memory Cell Layout Using Double Level Metallurgy

IP.com Disclosure Number: IPCOM000067027D
Original Publication Date: 1979-Jun-01
Included in the Prior Art Database: 2005-Feb-20

Publishing Venue

IBM

Related People

Authors:
Roberts, AL [+details]

Abstract

This dynamic 4-device memory cell is fabricated in metal-gate technology and uses two-levels of interconnect metallurgy to provide a compact cell in which stability problems caused by the beta ratio of the active, cross-coupled devices to the input/output devices are capable of being optimized for minimum cell size.