Decoder With Tri-State Output
Original Publication Date: 1979-Jun-01
Included in the Prior Art Database: 2005-Feb-20
This decoder circuit enables different voltages to be used independently on driven word lines in memory arrays in which independent control of word line potentials is required during times when a memory chip is not being accessed by the decoder. This condition is a requirement when asynchronous refreshing of dynamic memory cells is provided by refresh control circuitry independent from the decoders or whenever multiplexing of the decoder output is required.