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This is a technique for maintaining the same bit capacity within a basic storage module (BSM) by providing a partial-good substitution external to the defective memory components.
English (United States)
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Multiplexed Partial Good Chip Scheme Employing Defective Loops as
Selectors for All Good Chips
This is a technique for maintaining the same bit capacity within a basic
storage module (BSM) by providing a partial-good substitution external to the
defective memory components.
In CCD (charge-coupled device) memory applications, the storage is used in
a serial fashion as a block of data transfer device. As a result, the performance
criteria is based upon data rate instead of access time. This enables the memory
to be optimized on sustaining a performance after some period of time for
selection. Product yield enhancements can be obtained by using defective chips
in conjunction with all-good chips. This is accomplished by the substitution of the
all-good chip when a defective region of a chip is selected.
Fig. 1 shows a typical memory system employing error correction and
checking logic in a storage control unit where the data bus between this control
unit and memory arrays is multiplexed. The memory array units are selected,
addressed and controlled from this storage control unit.
The memory data bus is shown in Fig. 2 with multiple memory array units
multiplexed on a single data bus. The multiplexing is accomplished via individual
selects from the storage control units.
With memory arrays employing partial-good chips, a substitution of all-good
chips is used when the partial-good product is selected. This is normally done
within the memory array unit, making this tra...