Cache Bit Selection Circuit
Original Publication Date: 1979-Jun-01
Included in the Prior Art Database: 2005-Feb-20
The figure shows a sense amplifier/bit selection arrangement which retains the high performance, linear, differential sense amplifier feature used in prior schemes, but eliminates the bit select circuit as a stage of delay in the access path to the cache random-access memory. In addition, the circuit shown in the figure also eliminates the excessive power typically utilized in the bit selection circuit.