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Random Access Memory Cell For Medium Performance Applications

IP.com Disclosure Number: IPCOM000067077D
Original Publication Date: 1979-Jun-01
Included in the Prior Art Database: 2005-Feb-20

Publishing Venue

IBM

Related People

Authors:
Denis, BA Eardley, DB [+details]

Abstract

A circuit is disclosed for storing binary data in a random-access memory. The circuit diagram of the cell and the peripheral circuits for reading and writing data are shown in the figure. The cell consists of PNP transistors 11 and 12. inverted NPN transistors 13 and 14, normal NPN transistors 15, 16 and 17, Schottky barrier diodes 31 and 32, and resistor 41. The peripheral circuit for reading data consists of NPN transistors 19, 20, 21 and 22 and resistors 42, 43, 44 and 45. The voltage levels required to write the cell are applied to the data input lines DL and DR. By means of a select signal applied to the word line WL, one out of many cells is selected for reading or writing data.