Stacked Gate Device With Reduced "0" State Threshold Voltage
Original Publication Date: 1979-Jun-01
Included in the Prior Art Database: 2005-Feb-20
The threshold voltages V(T1) and V(T0) for "1" and "0" states of stacked-gate Floating-gate Avalanching Metal Oxide Silicon (FAMOS) devices the kind shown in the figure are given by: (Image Omitted) where C(C)=A(2) Epsilon ox/tox2 is the control gate capacitance. C(F) = A(1) Epsilon ox/tox1 is the floating gate capacitance. V(T) is the threshold voltage of an ordinary single poly device with gate oxide thickness = tox1 Q is the charge stored in the floating gate. tox1, A(1); tox2, A(2) are the oxide thickness and gate area of the floating gate and control gate, respectively. In a typical double poly FET process the oxide thickness between two polys is tox2 = 2.5 K Angstroms and tox1 = 500 Angstroms. Therefore, the "0" state threshold voltage (Image Omitted) if A(1) = A(2) is assumed.