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Emitter Coupled Logic Shift Register

IP.com Disclosure Number: IPCOM000067086D
Original Publication Date: 1979-Jun-01
Included in the Prior Art Database: 2005-Feb-20

Publishing Venue

IBM

Related People

Authors:
Suros, G Wolf, J [+details]

Abstract

Fig. 1 shows a prior emitter-coupled logic shift register cell. The cell consists of cross-coupled latches comprising transistors 12 and 13 and 22 and 23. Two differential amplifiers comprising transistors 11, 14 and 21, 24 provide inputs to the latches. The current steering differential amplifiers comprising transistors 15, 16 with their current source 17 and transistors 25, 26 with their current source 27 provide gating action to change the state of the latches only during the clock time.