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Branch Instruction Execution Sequence

IP.com Disclosure Number: IPCOM000067146D
Original Publication Date: 1979-Jun-01
Included in the Prior Art Database: 2005-Feb-20

Publishing Venue

IBM

Related People

Authors:
Hoffman, RL Kempke, WG Richardson, WC Soltis, FG [+details]

Abstract

In the past, computer systems have not detected address exceptions prior to completion of a branch operation and thereby required a previous instruction address register. The prior approach is illustrated in Fig. 1a. In the present arrangement, a dummy CPU cycle is used to provide time for completing address exception checks before updating the contents of the the Instruction Address Register (IAR), as illustrated in Fig. 1b.