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This article relates to a timed inverter circuit which has speeds and margins compatible with the current injection logic (CIL) family.
English (United States)
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Timed Inverter For Current Injection Logic
This article relates to a timed inverter circuit which has speeds and margins
compatible with the current injection logic (CIL) family.
A timed inverter circuit 1 is shown in Fig. 1, and the associated input and
output current pulses are shown in Fig. 2. Circuit 1 consists of two
interferometers D(1) and D(2) and an injection gate G of the type shown in U. S.
Patent 4,117,354. If Q = 1, interferometer D(1) switches, diverting the gate
current to resistor Rd. If a timing pulse T arrives later, as shown in Fig. 2,
interferometer D(2) will not switch because of its very low gate current. Thus, the
output will be "0". If Q = 0, then D(2) will switch when T = 1. This will inject
current into the nonlinear injection gate G, via resistor R(S). The gate G will
switch and deliver an output.
This inverter has a number of advantages such as a gate delay of about 30
ps for a serial fan-out of 3, a high gain > 3, and wide margins. It is completely
compatible with the CIL family since it uses the same devices. Also, it does not
require a bypass inductor to match the gate current to the control current.
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