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Long Line Receiver and Timing Circuits For Josephson Logic

IP.com Disclosure Number: IPCOM000067199D
Original Publication Date: 1979-Jun-01
Included in the Prior Art Database: 2005-Feb-20

Publishing Venue

IBM

Related People

Authors:
Klein, M [+details]

Abstract

Josephson logic circuits require relatively long transmission lines which carry logic signals which are transmitted from one chip and received on a remote chip. In latching logic, logic signals are relatively long rectangular pulses which terminate at the end of a logic cycle. When a logic signal generated on one chip during a logic cycle is received on a remote chip, the received signal may persist into the following logic cycle. These persistent signals must be prevented from causing false operation of the receiving devices when the next logic cycle starts. Circuits have been proposed for discriminating against such persistent or stored signals on the basis of the polarity change of the power supply occurring in successive logic cycles. These circuits have suffered from poor margins and poor noise immunity.